PLDs are a well-known type of integrated circuit that may be programmed to perform specified logic functions. One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAM), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs) and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and the programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these PLDs, the functionality of the device is controlled by configuration data bits provided to the device for that purpose. The configuration data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Some PLDs, such as the Xilinx Virtex® FPGA, can be programmed to incorporate blocks with pre-designed functionalities, i.e., “cores”. A core can include a predetermined set of configuration data bits that program the FPGA to perform one or more functions. Alternatively, a core can include source code or schematics that describe the logic and connectivity of a design. Typical cores can provide, but are not limited to, DSP functions, memories, storage elements, and math functions. Some cores include an optimally floor planned layout targeted to a specific family of FPGAs. Cores can also be parameterizable, i.e., allowing the user to enter parameters to activate or change certain core functionality.
Configuration, and/or full, or partial, reconfiguration of a PLD may be facilitated through dedicated configuration ports, and associated configuration control logic, which are tailored for ease of use, low cost, high flexibility, and backward compatibility. While these configuration ports provide adequate performance during configuration events that are not time critical, they are nevertheless inadequate for configuration events that are time critical.
A conventional configuration event of a PLD is one that is performed on the entire PLD after power-up. A full reconfiguration event, on the other hand, is one that is performed subsequent to a conventional configuration event.
A partial reconfiguration event may be accomplished subsequent to a conventional, or any type of reconfiguration, event, whereby only a portion of the PLD is reconfigured, while other portions of the PLD retain their current configuration. A partial reconfiguration event may also be accomplished dynamically, whereby the other portions of the PLD that retain their current configuration also remain active during reconfiguration of a portion of the PLD.
Each of the reconfiguration events, as discussed above however, are inadequate for time critical applications. For example, dynamic computing applications often require software controlled logic reconfiguration within hundreds of microseconds. Using known configuration techniques, however, the amount of time required for a typical reconfiguration event exceeds the dynamic computing requirements by at least an order of magnitude. That is to say, in other words, that the amount of time required to reconfigure a typical module during a partial reconfiguration event is on the order of several milliseconds, which is inadequate for dynamic computing applications.
One method to decrease the amount of time required for a reconfiguration event is to increase the dedicated configuration port's data width and the dedicated configuration port's data propagation rate. Such a method, however, would likely fail to decrease the amount of reconfiguration time to an acceptable level. Furthermore, such a method would increase the amount of dedicated configuration logic required within the PLD to support the increased configuration port width. Efforts continue, therefore, to obtain significant reduction in the amount of time required to complete a reconfiguration event.